1. Field of the Invention
This invention relates to the field of computer system architecture. More particularly, this invention relates to multiple bus architectures in a computer system.
2. Background
A typical computer system is comprised of a processor or CPU, a memory subsystem, an input/output subsystem, and other specialized subsystems. Communication between the processor and the subsystems is usually accomplished through one or more communication pathways known as buses. In many computer systems, the processor and subsystems are coupled for communication over a common bus.
As computer technology progresses, the performance of the processor and other subsystems improves. The improved performance in one subsystem creates the need for improved performance in the other subsystems. For example, as the performance of the processor improves, the memory or input/output subsystem is often redesigned to accommodate the improved processor performance. Similarly, as the performance of the memory subsystem improves, the processor architecture is changed to take advantage of the improved memory subsystem performance.
With the progressive performance improvements in processor, memory subsystem, and specialized subsystems, the communication pathways of the computer system often become the performance "bottlenecks." In past computer systems, the communication pathway architecture was designed in response to improvements to the processor and subsystems. The performance of such systems was not easily improved without redesigning the entire system including the communication pathways.
As will be described, the present multiple bus architecture provides flexible communication between processors, memory subsystems, and specialized subsystems over multiple high performance communication pathways. The high performance communication pathways enable communication for multiple processors and multiple subsystems, and enables flexible upgrade to higher performance processors and subsystems.